1. Field of the Invention
An embodiment of the present invention relates to the fabrication of interconnect structures in microelectronic devices. In particular, embodiments of the present invention relate to utilizing electroless deposition to fill narrow and high aspect ratio openings formed in dielectric layers during the fabrication of interconnect structures.
2. State of the Art
The fabrication of microelectronic devices involves forming electronic components on microelectronic substrates, such as silicon wafers. These electronic components may include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the electrical components to form integrated circuits. The metallization patterns are generally referred to as “interconnects”.
One process used to form interconnects is known as a “damascene process”. In a typical damascene process, a photoresist material is patterned on a dielectric material and the dielectric material is etched through the photoresist material patterning to form a hole or a trench (hereinafter collectively referred to as “an opening” or “openings”). The photoresist material is then removed (typically by an oxygen plasma) and the opening is then filled with a conductive material (e.g., such as a metal or metal alloys). The filling of the opening may be accomplished by either physical vapor deposition, chemical vapor deposition, or electroplating, as will be understood to those skilled in the art. When the opening is a hole, the resulting filled structure is referred to herein as a “via”. When the opening is a trench, the resulting filled structure is referred to herein as a “trace”. The term “interconnect” is defined herein to include all interconnection components including traces and vias.
An optional barrier layer may be disposed on the dielectric material within the opening to prevent diffusion of the conductive material. Additionally, an optional seed layer may be disposed on the barrier layer, if present, or on the dielectric layer, if no barrier layer is present, to assist in the deposition of the conductive material, particularly when an electroplating deposition process is utilized.
The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP) or by an etching process, which removes the conductive material, which is not within the opening, from the surface of the dielectric material, to form the interconnect. As is understood by those skilled in the art, a variety of vias and traces may be formed in the various dielectric material layers to electrically connect to one another and/or to various electronic components. In another damascene process, known as a “dual damascene process”, trenches and vias are substantially simultaneously filled with the conductive material with a single deposition.
As the density of integrated circuits within microelectronic devices continues to increase with each successive technology generation, the interconnects become smaller and their aspect ratios (i.e., the ratio of depth to width) may increase. As shown in FIGS. 16 and 17, a problem with small size and/or high aspect ratios is that a conductive material 402 can build up at an opening 404 proximate a first surface 406 of a dielectric material 408 (i.e., the “mouth” 412 of the opening 404) during deposition. An optional barrier layer 410 may also be present, as will be understood to those skilled in the art.
The build-up (illustrated within dashed circle 414) blocks the path of the deposited conductive material 402 and, as shown in FIG. 18, can result in voids 416 forming within the conductive material 402 in the opening 404 (shown in FIGS. 16 and 17). FIG. 18 illustrates an interconnect 418 formed after the conductive material 402, which is not within the opening 404 (shown in FIG. 16), from the dielectric material first surface 406. The voids 416 can have different sizes, distributions, and locations within the interconnect 418. For example, some voids 416 may be so large that they effectively break the conductive path of the interconnect 418, which may result in the failure of the microelectronic device, thereby having an immediate impact on yield. Additionally, the voids 416 may also be small, which may have an immediate impact by restricting the flow of electrons along the interconnect 418 and/or may have a negative impact on the long-term reliability of the microelectronic device.
Current conductive material deposition techniques are non-selective, relatively costly, and are susceptible to voiding, particularly with opening having widths of between about 2 and 15 nanometers with aspect ratios of between about 1 and 15. Additionally, using electroplating techniques in the filling of openings may also have issues with regard to metal corrosion due to long nucleation times, as well as bath stability and particle generation, as will be understood to those skilled in the art.
Therefore, it would be advantageous to develop techniques to effectively fill openings, while reducing or substantially eliminating void formation during the fabrication of interconnects for microelectronic devices.